1. Field
This disclosure relates generally to integrated circuits, and more specifically, to an integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor.
2. Related Art
Floating gate non-volatile memories such as erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), block erasable (“flash”) EEPROMs, and one time programmable read only memories (OTPROMs) are popular for many electronic applications such as automotive control, consumer products such as tapeless answering machines, and the like. In floating gate memories, the state of each memory cell is determined by the amount of charge stored on a floating gate. The floating gate is isolated from an underlying channel by a region of tunnel oxide. Typically, the floating gate transistor is programmed and erased by processes known as Fowler-Nordheim tunneling and hot carrier injection. One process that uses Fowler-Nordheim tunneling for erasing a flash memory is called “channel erase”.
A typical flash memory cell manufactured using a “triple well” process may have five terminals that must be properly biased for program and erase operations: a control gate, a source, a drain, a P-well terminal, and a deep N-well terminal. An array of flash memory cells is formed in the P-well. The P-well is isolated within the deep N-well. One technique for performing a channel erase operation on the memory cells of the flash memory array involves applying a relatively high negative voltage, for example about −9 volts, to the control gate, while applying a relatively high positive voltage, for example about +9 volts, to the P-well and the deep N-well. The drain and source of the memory cell are allowed to “float”, that is, the drain and source are not directly coupled to a source of potential. However, due to capacitive coupling between the five terminals around the floating gate as well as the diode formed between the drain/source and P-well, the drain and source may float no lower than a diode drop below the P-well/deep N-well voltage.
At the end of an erase operation, the voltage on the five terminals is discharged. If the terminals are allowed to discharge too quickly, an effect of discharging the relatively high negative voltage on the control gate can cause drain, source, and P-well potentials to peak at a voltage higher than 10 volts because of the capacitive coupling. The circuit may see potentials to −10 volts on the control gate due to capacitive coupling. The application of a voltage higher than 10 volts may cause the gate oxide of high voltage transistors connected to the nodes of the memory cells to break down, drain source punch through of the transistors connected to the nodes of the memory cell, or other forms of high voltage damage, thus shortening the life of the flash memory.
What would be desirable therefore are a method, and a non-volatile memory using such a method, which prevents the exposure of the high voltage transistors to high voltage beyond the reliability limits. Such a method and a non-volatile memory using that technique is provided by the embodiments of the present disclosure, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.